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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 1 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
EDOC
2009
IEEE
14 years 2 months ago
Using Enterprise Architecture Management Patterns to Complement TOGAF
—The design of an Enterprise Architecture (EA) management function for an enterprise is no easy task. Various frameworks exist as well as EA management tools, which promise to de...
Sabine Buckl, Alexander M. Ernst, Florian Matthes,...
ANCS
2007
ACM
13 years 12 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy
CHI
1998
ACM
14 years 6 days ago
The Vista Environment for the Coevolutionary Design of User Interfaces
User centered design requires the creation of numerous design artifacts such as task hierarchy, task-oriented specification, user interface design, architecture design and code. I...
Judy Brown, T. C. Nicholas Graham, Timothy N. Wrig...
DAC
2000
ACM
14 years 10 days ago
Using general-purpose programming languages for FPGA design
ct General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both t...
Brad L. Hutchings, Brent E. Nelson