Sciweavers

182 search results - page 23 / 37
» A distributed processor state management architecture for la...
Sort
View
ICSE
2001
IEEE-ACM
14 years 5 days ago
A Web-Oriented Architectural Aspect for the Emerging Computational Tapestry
An emerging tapestry of computations will soon integrate systems around the globe. It will evolve without central control. Its complexity will be vast. We need new ideas, tools an...
Kevin J. Sullivan, Avneesh Saxena
WMPI
2004
ACM
14 years 1 months ago
A localizing directory coherence protocol
User-controllable coherence revives the idea of cooperation between software and hardware in an attempt to bridge the gap between efficient small-scale shared memory machines and m...
Collin McCurdy, Charles N. Fischer
HPCA
2004
IEEE
14 years 8 months ago
Hardware Support for Prescient Instruction Prefetch
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wan...
HPCA
2004
IEEE
14 years 8 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel
CLUSTER
2009
IEEE
14 years 13 days ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis