496 search results - page 19 / 100 » A formal framework for synthesis and verification of logic p... |
JACM
2002
13 years 7 months ago
2002
We show how to use an interactive theorem prover, HOL, together with a model checker, SPIN, to prove key properties of distance vector routing protocols. We do three case studies: ...
ICIW
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract-- Maintaining large websites and verifying their semantic content is a difficult task. In this paper we propose a framework for syntactic validation, semantic verification...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
ENTCS
2008
13 years 7 months ago
2008
Thanks to recent advances, modern proof assistants now enable verification of realistic sequential programs. However, regarding the concurrency paradigm, previous work essentially...
ATAL
2008
Springer
13 years 9 months ago
2008
Springer
We explore the problem of specification and verification of compliance in agent based Web service compositions. We use the formalism of temporal-epistemic logic suitably extended ...