496 search results - page 20 / 100 » A formal framework for synthesis and verification of logic p... |
SAC
2010
ACM
13 years 5 months ago
2010
ACM
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
CADE
2009
Springer
14 years 8 months ago
2009
Springer
Scalable handling of real arithmetic is a crucial part of the verification of hybrid systems, mathematical algorithms, and mixed analog/digital circuits. Despite substantial advanc...
POPL
2006
ACM
14 years 8 months ago
2006
ACM
Traditional static type systems are very effective for verifying basic interface specifications, but are somewhat limited in the kinds specificationsthey support. Dynamically-chec...
ICFP
2006
ACM
14 years 7 months ago
2006
ACM
In previous work, we proposed a Hoare Type Theory (HTT) which combines effectful higher-order functions, dependent types and Hoare Logic specifications into a unified framework. H...