171 search results - page 3 / 35 » A framework for evaluating design tradeoffs in packet proces... |
SIGCOMM
2010
ACM
13 years 7 months ago
2010
ACM
We present PacketShader, a high-performance software router framework for general packet processing with Graphics Processing Unit (GPU) acceleration. PacketShader exploits the mas...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
PARELEC
2006
IEEE
14 years 1 months ago
2006
IEEE
We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we h...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we empirically evaluate fundamental design trade-offs among the most recent multicore processors and accelerator technologies. Our primary aim is to aid application...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...