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» A functional formalization of on chip communications
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MEMOCODE
2007
IEEE
14 years 1 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
IEEEPACT
2008
IEEE
14 years 1 months ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...
ICC
2007
IEEE
14 years 1 months ago
Power Managed Packet Switching
— High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 25 days ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
INFOCOM
2005
IEEE
14 years 11 days ago
TCAM-based distributed parallel packet classification algorithm with range-matching solution
Packet Classification (PC) has been a critical data path function for many emerging networking applications. An interesting approach is the use of TCAM to achieve deterministic, hi...
Kai Zheng, Hao Che, Zhijun Wang, Bin Liu