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IPPS
2000
IEEE
14 years 10 hour ago
Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards
This paper examines two Network Interface Card microarchitectures that support low latency, high bandwidth userlevel message passing in multi-user environments. The two are at dif...
Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind
ICDCS
2009
IEEE
13 years 5 months ago
The Case for Spam-Aware High Performance Mail Server Architecture
The email volume per mailbox has largely remained low and unchanged in the past several decades, and hence mail server performance has largely remained a secondary issue. The stee...
Abhinav Pathak, Syed Ali Raza Jafri, Y. Charlie Hu
ACSC
2005
IEEE
14 years 1 months ago
A High Performance Kernel-Less Operating System Architecture
Operating Systems provide services that are accessed by processes via mechanisms that involve a ring transition to transfer control to the kernel where the required function is pe...
Amit Vasudevan, Ramesh Yerraballi, Ashish Chawla
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 5 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
RTCSA
2007
IEEE
14 years 1 months ago
MB++: An Integrated Architecture for Pervasive Computing and High-Performance Computing
MB++ is a system that caters to the dynamic needs of applications in a distributed, pervasive computing environment that has a wide variety of devices that act as producers and co...
David J. Lillethun, David Hilley, Seth Horrigan, U...