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CATA
2004
13 years 11 months ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki
ICIP
2009
IEEE
14 years 10 months ago
Mapping Motion Vectors For A Wyner-ziv Video Transcoder
Wyner-Ziv (WZ) coding of video utilizes simple encoders and highly complex decoders. A transcoder from a WZ codec to a traditional codec can potentially increase the range of appl...
ICCD
2005
IEEE
107views Hardware» more  ICCD 2005»
14 years 6 months ago
Hardware Support for Bulk Data Movement in Server Platforms
Bulk data movement occurs commonly in server workloads and their performance is rather poor on today’s microprocessors. We propose the use of small dedicated copy engines, and p...
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. ...
ISCAS
2006
IEEE
99views Hardware» more  ISCAS 2006»
14 years 3 months ago
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor
— By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error ra...
Hao Zhong, Tong Zhang, Erich F. Haratsch
PEWASUN
2004
ACM
14 years 3 months ago
A modified IEEE 802.11 MAC protocol for MC-CDMA
In this paper, we introduce a modified version of the IEEE 802.11a protocol and evaluate its performance. The new protocol is a combination of the standard Medium Access Control (...
Georgios Orfanos, Jörg Habetha, Ling Liu