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» A high performance JPEG2000 architecture
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VLSISP
1998
128views more  VLSISP 1998»
13 years 9 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
TPDS
2002
105views more  TPDS 2002»
13 years 9 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
WD
2010
13 years 7 months ago
Content Centric Networking in tactical and emergency MANETs
Abstract--Reliable and secure content distribution in a disruptive environment is a critical challenge due to high mobile and lossy channels. Traditional IP networking and wireless...
Soon-Young Oh, Davide Lau, Mario Gerla
UBIMOB
2009
ACM
225views Management» more  UBIMOB 2009»
14 years 2 months ago
Historical data storage for large scale sensor networks
Wireless sensor networks are rapidly finding their way through a plethora of new applications like precision farming and forestry, with increasing network scale, system complexit...
Loïc Petit, Abdelhamid Nafaa, Raja Jurdak
JSA
2010
158views more  JSA 2010»
13 years 4 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...