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DAC
2009
ACM
14 years 8 months ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...
ISPA
2004
Springer
14 years 27 days ago
Cayley DHTs - A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
Changtao Qu, Wolfgang Nejdl, Matthias Kriesell
JSA
2002
125views more  JSA 2002»
13 years 7 months ago
Building a dependable system from a legacy application with CORBA
This paper presents a dependability oriented, fault tolerance based system design, development, and deployment approach. The approach relies on an architectural framework, which a...
Domenico Cotroneo, Nicola Mazzocca, Luigi Romano, ...
IEEECIT
2010
IEEE
13 years 6 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
14 years 1 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel