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ICASSP
2010
IEEE
13 years 9 months ago
Power law discounting for n-gram language models
We present an approximation to the Bayesian hierarchical PitmanYor process language model which maintains the power law distribution over word tokens, while not requiring a comput...
Songfang Huang, Steve Renals
DAC
2002
ACM
14 years 10 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
MR
2006
118views Robotics» more  MR 2006»
13 years 9 months ago
Single event burnout in power diodes: Mechanisms and models
Power electronic devices are susceptible to catastrophic failures when they are exposed to energetic particles; the most serious failure mechanism is single event burnout (SEB). S...
A. M. Albadri, Ronald D. Schrimpf, Kenneth F. Gall...
DAC
2003
ACM
14 years 10 months ago
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact wi...
Dexin Li, Qiang Xie, Pai H. Chou
IBMRD
2006
76views more  IBMRD 2006»
13 years 9 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
Nicholas P. Carter, Azmat Hussain