77 search results - page 9 / 16 » A new cache architecture based on temporal and spatial local... |
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
ICS
2004
Tsinghua U.
14 years 29 days ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
CF
2005
ACM
13 years 9 months ago
2005
ACM
In this paper, we consider alternate ways of storing a sparse matrix and their effect on computational speed. They involve keeping both the indices and the non-zero elements in t...
EUROPAR
2005
Springer
14 years 1 months ago
2005
Springer
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...
PDCN
2004
13 years 9 months ago
2004
We present a family of methods for speeding up distributed locks by exploiting the uneven distribution of both temporal and spatial locality of access behaviour of many applicatio...