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JPDC
2000
141views more  JPDC 2000»
13 years 9 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
CADE
1998
Springer
14 years 1 months ago
System Description: card TAP: The First Theorem Prover on a Smart Card
Abstract. We present the first implementation of a theorem prover running on a smart card. The prover is written in Java and implements a dual tableau calculus. Due to the limited ...
Rajeev Goré, Joachim Posegga, Andrew Slater...
ISPASS
2010
IEEE
14 years 4 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
OOPSLA
2010
Springer
13 years 8 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
SIGDOC
2005
ACM
14 years 3 months ago
Metadata based authoring for technical documentation
The creation process of technical documentation is an expensive and time-consuming task especially for complex products. To make this process more cost-efficient computerized supp...
Ingo Stock, Michael Weber, Eckhard Steinmeier