41 search results - page 6 / 9 » A novel FPGA logic block for improved arithmetic performance |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
CADE
2007
Springer
14 years 8 months ago
2007
Springer
We present a novel reasoning calculus for Description Logics (DLs)--knowledge representation formalisms with applications in areas such as the Semantic Web. In order to reduce the ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...