Sciweavers

121 search results - page 6 / 25
» A novel deadlock avoidance algorithm and its hardware implem...
Sort
View
TC
2008
13 years 7 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
IEEEPACT
2007
IEEE
14 years 1 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
JRTIP
2007
108views more  JRTIP 2007»
13 years 7 months ago
Real-time hardware acceleration of the trace transform
The trace transform is a novel algorithm that has been shown to be effective in a number of image recognition tasks. It is a generalisation of the Radon transform that has been wid...
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y...
STTT
2010
97views more  STTT 2010»
13 years 6 months ago
Distributed dynamic partial order reduction
Abstract. Runtime (dynamic) model checking is a promising verification methodology for real-world threaded software because of its many features, the prominent ones being: (i) it ...
Yu Yang, Xiaofang Chen, Ganesh Gopalakrishnan, Rob...
ASPDAC
2006
ACM
173views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking
A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With ...
K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tet...