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» A novel high throughput reconfigurable FPGA architecture
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ERSA
2008
145views Hardware» more  ERSA 2008»
13 years 9 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 1 months ago
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform
In this paper, the EX-VPR tool, which used for architecture level exploration, is presented. This tool belongs to an integrated framework (MEANDER) for mapping applications into a...
K. Siozios, Konstantinos Tatas, George Koutroumpez...
FPL
2006
Springer
135views Hardware» more  FPL 2006»
13 years 11 months ago
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
Luis G. Barbero, John S. Thompson
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
14 years 1 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
FPGA
2007
ACM
119views FPGA» more  FPGA 2007»
14 years 1 months ago
Synthesis of an application-specific soft multiprocessor system
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
Jason Cong, Guoling Han, Wei Jiang