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» A novel high throughput reconfigurable FPGA architecture
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MAM
2007
113views more  MAM 2007»
13 years 8 months ago
A reconfigurable computing framework for multi-scale cellular image processing
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Ha...
ASAP
2006
IEEE
124views Hardware» more  ASAP 2006»
13 years 10 months ago
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers
This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. I...
Daesun Oh, Keshab K. Parhi
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
14 years 2 months ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...
RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
14 years 3 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
ICDE
2011
IEEE
234views Database» more  ICDE 2011»
13 years 5 days ago
Massively parallel XML twig filtering using dynamic programming on FPGAs
Abstract— In recent years, XML-based Publish-Subscribe Systems have become popular due to the increased demand of timely event-notification. Users (or subscribers) pose complex ...
Roger Moussalli, Mariam Salloum, Walid A. Najjar, ...