252 search results - page 36 / 51 » A novel high throughput reconfigurable FPGA architecture |
FPL
2009
Springer
14 years 1 months ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing...
TIFS
2008
13 years 8 months ago
2008
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
ARC
2008
Springer
13 years 10 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
ANCS
2009
ACM
13 years 6 months ago
2009
ACM
Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and ...