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» A novel high throughput reconfigurable FPGA architecture
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ANCS
2009
ACM
13 years 6 months ago
Experience with high-speed automated application-identification for network-management
AtoZ, an automatic traffic organizer, provides control of how network-resources are used by applications. It does this by combining the high-speed packet processing of the NetFPGA...
Marco Canini, Wei Li 0009, Martin Zádn&iacu...
HIPEAC
2010
Springer
14 years 22 days ago
Accelerating XML Query Matching through Custom Stack Generation on FPGAs
Abstract. Publish-subscribe systems present the state of the art in information dissemination to multiple users. Such systems have evolved from simple topic-based to the current XM...
Roger Moussalli, Mariam Salloum, Walid A. Najjar, ...
CODES
2003
IEEE
14 years 2 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
JUCS
2007
104views more  JUCS 2007»
13 years 8 months ago
Real-time Architecture for Robust Motion Estimation under Varying Illumination Conditions
: Motion estimation from image sequences is a complex problem which requires high computing resources and is highly affected by changes in the illumination conditions in most of th...
Javier Díaz, Eduardo Ros, Rafael Rodr&iacut...
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 1 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá