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» A novel high throughput reconfigurable FPGA architecture
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INFOCOM
2006
IEEE
14 years 2 months ago
The Concurrent Matching Switch Architecture
Abstract— Network operators need high capacity router architectures that can offer scalability, provide throughput guarantees, and maintain packet ordering. However, current cent...
Bill Lin, Isaac Keslassy
DAC
2009
ACM
14 years 1 months ago
A computing origami: folding streams in FPGAs
Stream processing represents an important class of applications that spans telecommunications, multimedia and the Internet. The implementation of streaming programs in FPGAs has a...
Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Ro...
ISCAS
2008
IEEE
127views Hardware» more  ISCAS 2008»
14 years 3 months ago
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection
— ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC imple...
Huiju Cheng, Howard M. Heys
SAMOS
2005
Springer
14 years 2 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
CF
2009
ACM
14 years 3 months ago
Wave field synthesis for 3D audio: architectural prospectives
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, G...