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» A novel high throughput reconfigurable FPGA architecture
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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 2 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
14 years 2 months ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...
FPL
2008
Springer
178views Hardware» more  FPL 2008»
13 years 10 months ago
High-speed regular expression matching engine using multi-character NFA
An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which a...
Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kam...
HIPC
2009
Springer
13 years 6 months ago
Highly scalable algorithm for distributed real-time text indexing
Stream computing research is moving from terascale to petascale levels. It aims to rapidly analyze data as it streams in from many sources and make decisions with high speed and a...
Ankur Narang, Vikas Agarwal, Monu Kedia, Vijay K. ...
DAC
2006
ACM
14 years 9 months ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner