359 search results - page 64 / 72 » A section cache system designed for VLIW architectures |
SIGGRAPH
1994
ACM
14 years 1 months ago
1994
ACM
Virtual reality systems are placing never before seen demands on computer graphics hardware, yet few graphics systems are designed specifically for virtual reality. An address rec...
CODES
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
GCC
2004
Springer
14 years 2 months ago
2004
Springer
Real-time rendering of complex 3D scene on mobile devices is a challenging task. The main reason is that mobile devices have limited computational capabilities and are lack of powe...
ANCS
2007
ACM
14 years 1 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
ISCA
1997
IEEE
14 years 1 months ago
1997
IEEE
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...