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GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
14 years 1 months ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou
FCCM
1999
IEEE
111views VLSI» more  FCCM 1999»
13 years 12 months ago
Optimizing FPGA-Based Vector Product Designs
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
Dan Benyamin, John D. Villasenor, Wayne Luk
DAC
1995
ACM
13 years 11 months ago
New Performance-Driven FPGA Routing Algorithms
—Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions signiï...
Michael J. Alexander, Gabriel Robins
COMCOM
2010
246views more  COMCOM 2010»
13 years 6 months ago
Tabu search algorithm for RP selection in PIM-SM multicast routing
: - To construct a multicast tree is the basis of multicast data transmission. The prime problem concerning the construction of a shared multicast tree is to determine the position...
Hua Wang, Xiangxu Meng, Min Zhang, Yanlong Li
ICCNMC
2005
Springer
14 years 1 months ago
Hierarchical Multicast Tree Algorithms for Application Layer Mesh Networks
This paper proposes a set of novel multicast algorithms for m-D mesh overlay networks that can achieve shorter multicast delay and less resource consumptions. In contrast to previo...
Weijia Jia, Wanqing Tu, Jie Wu