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DAC
2006
ACM
13 years 10 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
IWCC
1999
IEEE
14 years 1 months ago
Single I/O Space for Scalable Cluster Computing
In this paper, we propose a novel Single I/O Space architecture for achieving a Single System Image (SSI) at the I/O subsystem level. This is very much desired in a scalable clust...
Roy S. C. Ho, Hai Jin, Kai Hwang
CODES
2008
IEEE
13 years 9 months ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
MTA
2006
115views more  MTA 2006»
13 years 8 months ago
Cache modeling and optimization for portable devices running MPEG-4 video decoder
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...
Abu Asaduzzaman, Imad Mahgoub
CF
2010
ACM
14 years 1 days ago
A communication infrastructure for a million processor machine
: The SpiNNaker machine is a massively parallel computing system, consisting of 1,000,000 cores. From one perspective, it has a place in Flynns' taxonomy: it is a straightforw...
Andrew D. Brown, Steve Furber, Jeff S. Reeve, Pete...