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CODES
2008
IEEE
13 years 9 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
SPIN
2004
Springer
14 years 27 days ago
Model-Driven Software Verification
Abstract. In the classic approach to logic model checking, software verification requires a manually constructed artifact (the model) to be written in the language that is accepted...
Gerard J. Holzmann, Rajeev Joshi
MSCS
2008
97views more  MSCS 2008»
13 years 7 months ago
Logical relations for monadic types
Abstract. Software security can be ensured by specifying and verifying security properties of software using formal methods with strong theoretical bases. In particular, programs c...
Jean Goubault-Larrecq, Slawomir Lasota, David Nowa...
SCSC
2007
13 years 9 months ago
A graphical variant approach to object-oriented modeling of dynamic systems
Abstract— Graphical variant modeling refers to a novel approach to object-oriented modeling whereby a class overrides behavior inherited from a parent class by specifying variati...
Paul Kinnucan, Pieter J. Mosterman
ASWEC
2006
IEEE
14 years 1 months ago
Formal Verification of the IEEE 802.11i WLAN Security Protocol
With the increased usage of wireless LANs (WLANs), businesses and educational institutions are becoming more concerned about wireless network security. The latest WLAN security pr...
Elankayer Sithirasenan, Saad Zafar, Vallipuram Mut...