1279 search results - page 253 / 256 » AWESIM: The Integrated Simulation System |
CF
2007
ACM
13 years 11 months ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
ICRA
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper describes the progress of the BIP2000 project. This project, in which four laboratories are involved for 4 years, as uimed at the realization of the lower part of an an...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
NSDI
2004
13 years 8 months ago
2004
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
BMCBI
2010
13 years 7 months ago
2010
Background: The accumulation of high-throughput data greatly promotes computational investigation of gene function in the context of complex biological systems. However, a biologi...