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ARC
2009
Springer
175views Hardware» more  ARC 2009»
14 years 2 months ago
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
Brendan P. Glackin, Jim Harkin, T. Martin McGinnit...
CASES
2009
ACM
14 years 1 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
IPPS
2010
IEEE
13 years 5 months ago
A GPU-inspired soft processor for high-throughput acceleration
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...
Jeffrey Kingyens, J. Gregory Steffan
PDP
2011
IEEE
12 years 11 months ago
Accelerating Parameter Sweep Applications Using CUDA
—This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications w...
Masaya Motokubota, Fumihiko Ino, Kenichi Hagihara
ASAP
2008
IEEE
186views Hardware» more  ASAP 2008»
14 years 1 months ago
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-thro...
Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberla...