Sciweavers

41 search results - page 5 / 9
» Access Region Locality for High-Bandwidth Processor Memory S...
Sort
View
HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
WMPI
2004
ACM
14 years 1 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
CF
2004
ACM
14 years 1 months ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...
ASPLOS
2006
ACM
14 years 1 months ago
Stealth prefetching
Prefetching in shared-memory multiprocessor systems is an increasingly difficult problem. As system designs grow to incorporate larger numbers of faster processors, memory latency...
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
HPDC
1999
IEEE
14 years 1 days ago
Dodo: A User-level System for Exploiting Idle Memory in Workstation Clusters
In this paper, we present the design and implementation of Dodo, an e cient user-level system for harvesting idle memory in o -the-shelf clusters of workstations. Dodo enables dat...
Samir Koussih, Anurag Acharya, Sanjeev Setia