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VLSISP
2008
95views more  VLSISP 2008»
13 years 6 months ago
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
Tsu-Ming Liu, Chen-Yi Lee
LCTRTS
2010
Springer
14 years 1 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
CODES
2001
IEEE
13 years 10 months ago
Compiler-directed selection of dynamic memory layouts
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
Mahmut T. Kandemir, Ismail Kadayif
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
13 years 11 months ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...
CASCON
1996
114views Education» more  CASCON 1996»
13 years 8 months ago
Modeling on-line rebalancing with priorities and executing on parallel database systems
Because changes to the database (DB) and workload occur during a DB system's lifetime, the physical DB design must evolve to sustain good performance. These changes are carri...
Daniel C. Zilio