Sciweavers

11384 search results - page 23 / 2277
» Achieved IPC Performance
Sort
View
BROADNETS
2007
IEEE
14 years 3 months ago
Scheduling routing table calculations to achieve fast convergence in OSPF protocol
Fast convergence to topology changes is a key requirement in modern routing infrastructure while reducing the protocol CPU overhead continues to be as important as before. In this...
Mukul Goyal, Weigao Xie, Mohd Soperi, Seyed H. Hos...
ISPASS
2010
IEEE
14 years 3 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 3 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ICS
2003
Tsinghua U.
14 years 1 months ago
Reducing register ports using delayed write-back queues and operand pre-fetch
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
Nam Sung Kim, Trevor N. Mudge
FPGA
2004
ACM
140views FPGA» more  FPGA 2004»
14 years 11 days ago
Using reconfigurability to achieve real-time profiling for hardware/software codesign
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...
Lesley Shannon, Paul Chow