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CAINE
2003
13 years 10 months ago
An Issue Logic for Superscalar Microprocessors
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
Feng-Jiann Shiao, Jong-Jiann Shieh
GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 6 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...
EUROPAR
2005
Springer
14 years 2 months ago
Improving Instruction Delivery with a Block-Aware ISA
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
Ahmad Zmily, Earl Killian, Christos Kozyrakis
HPDC
1993
IEEE
14 years 25 days ago
A Parallel Object-Oriented Framework for Stencil Algorithms
Wepresent an object-oriented framework for constructing parallel implementations of stencil algorithms. This framework simplifres the development process by encapsulating the comm...
John F. Karpovich, Matthew Judd, W. Timothy Straye...
CF
2008
ACM
13 years 10 months ago
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components--including registers, function...
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, ...