144 search results - page 8 / 29 » Adapting cache line size to application behavior |
LCTRTS
2009
Springer
14 years 2 months ago
2009
Springer
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
ICCS
2005
Springer
14 years 28 days ago
2005
Springer
Abstract. The increasing gap of processor and main memory performance underlines the need for cache-optimizations, especially on memoryintensive applications. Tools which are able ...
ISPASS
2008
IEEE
14 years 1 months ago
2008
IEEE
The floating point portion of the SPEC CPU suite and the HPC Challenge suite are widely recognized and utilized as benchmarks that represent scientific application behavior. In th...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...