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VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 8 months ago
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit C...
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 7 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
ICPR
2008
IEEE
14 years 8 months ago
Clothes-invariant gait identification using part-based adaptive weight control
This paper describes a method of part-based gait identification under substantial clothes variations. When clothes types between a gallery and a probe are different, silhouettes f...
Md. Altab Hossain, Wang Junqui, Yasushi Makihara, ...
AUTOMATICA
2008
78views more  AUTOMATICA 2008»
13 years 7 months ago
Multi-modal control using adaptive motion description languages
In this paper, we address the problem of adaptively enriching motion description languages for multi-modal control by systematically enlarging the set of available modes. This pro...
Tejas R. Mehta, Magnus Egerstedt
DAC
2009
ACM
14 years 8 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...