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» Address generation for memories containing multiple arrays
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SIGGRAPH
1996
ACM
13 years 11 months ago
Light Field Rendering
A number of techniques have been proposed for flying through scenes by redisplaying previously rendered or digitized views. Techniques have also been proposed for interpolating be...
Marc Levoy, Pat Hanrahan
HPCA
2009
IEEE
14 years 8 months ago
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems
Linked data structure (LDS) accesses are critical to the performance of many large scale applications. Techniques have been proposed to prefetch such accesses. Unfortunately, many...
Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 2 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 7 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
BMCBI
2008
133views more  BMCBI 2008»
13 years 7 months ago
Towards ontology-driven navigation of the lipid bibliosphere
Background: The indexing of scientific literature and content is a relevant and contemporary requirement within life science information systems. Navigating information available ...
Christopher J. O. Baker, Kanagasabai Rajaraman, We...