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» Address generation for memories containing multiple arrays
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ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 9 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
BMCBI
2008
181views more  BMCBI 2008»
13 years 6 months ago
Assessing batch effects of genotype calling algorithm BRLMM for the Affymetrix GeneChip Human Mapping 500 K array set using 270
Background: Genome-wide association studies (GWAS) aim to identify genetic variants (usually single nucleotide polymorphisms [SNPs]) across the entire human genome that are associ...
Huixiao Hong, Zhenqiang Su, Weigong Ge, Leming M. ...
ICDM
2008
IEEE
141views Data Mining» more  ICDM 2008»
14 years 1 months ago
Scalable Tensor Decompositions for Multi-aspect Data Mining
Modern applications such as Internet traffic, telecommunication records, and large-scale social networks generate massive amounts of data with multiple aspects and high dimensiona...
Tamara G. Kolda, Jimeng Sun
PPOPP
2010
ACM
14 years 4 months ago
Symbolic prefetching in transactional distributed shared memory
We present a static analysis for the automatic generation of symbolic prefetches in a transactional distributed shared memory. A symbolic prefetch specifies the first object to be...
Alokika Dash, Brian Demsky
ATS
2009
IEEE
127views Hardware» more  ATS 2009»
14 years 17 days ago
On the Generation of Functional Test Programs for the Cache Replacement Logic
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
Wilson J. Perez, Danilo Ravotto, Edgar E. Sá...