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DAC
2005
ACM
13 years 9 months ago
Normalization at the arithmetic bit level
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) descriptio...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
ICCD
1995
IEEE
109views Hardware» more  ICCD 1995»
13 years 11 months ago
Verifying the performance of the PCI local bus using symbolic techniques
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
Sérgio Vale Aguiar Campos, Edmund M. Clarke...
SIGSOFT
2003
ACM
14 years 8 months ago
Towards scalable compositional analysis by refactoring design models
Automated finite-state verification techniques have matured considerably in the past several years, but state-space explosion remains an obstacle to their use. Theoretical lower b...
Yung-Pin Cheng, Michal Young, Che-Ling Huang, Chia...
FASE
2006
Springer
13 years 11 months ago
Formal Simulation and Analysis of the CASH Scheduling Algorithm in Real-Time Maude
This paper describes the application of the Real-Time Maude tool to the formal specification and analysis of the CASH scheduling algorithm and its suggested modifications. The CASH...
Peter Csaba Ölveczky, Marco Caccamo