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» Aggregating processor free time for energy reduction
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RTAS
2003
IEEE
14 years 23 days ago
Collaborative Operating System and Compiler Power Management for Real-Time Applications
Managing energy consumption has become vitally important to battery operated portable and embedded systems. A dynamic voltage scaling (DVS) technique reduces the processor’s dyn...
Nevine AbouGhazaleh, Daniel Mossé, Bruce R....
CODES
2011
IEEE
12 years 7 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
HPCA
2012
IEEE
12 years 3 months ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
IPPS
2005
IEEE
14 years 1 months ago
Scheduling Processor Voltage and Frequency in Server and Cluster Systems
Modern server farm and cluster sites consume large quantities of energy both to power and cool the machines in the site. At the same time, less power supply redundancy is offered ...
Ramakrishna Kotla, Soraya Ghiasi, Tom W. Keller, F...
CODES
2009
IEEE
13 years 8 months ago
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
Mohammad Ali Ghodrat, Tony Givargis