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PC
2007
161views Management» more  PC 2007»
13 years 7 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
PRDC
2006
IEEE
14 years 1 months ago
Fault-Tolerant Partitioning Scheduling Algorithms in Real-Time Multiprocessor Systems
This paper presents the performance analysis of several well-known partitioning scheduling algorithms in real-time and fault-tolerant multiprocessor systems. Both static and dynam...
Hakem Beitollahi, Geert Deconinck
HPCC
2007
Springer
14 years 1 months ago
Improving a Fault-Tolerant Routing Algorithm Using Detailed Traffic Analysis
Currently, some coarse measures like global network latency are used to compare routing protocols. These measures do not provide enough insight of traffic distribution among networ...
Abbas Nayebi, Arash Shamaei, Hamid Sarbazi-Azad
SBCCI
2006
ACM
124views VLSI» more  SBCCI 2006»
14 years 1 months ago
A cryptography core tolerant to DFA fault attacks
This work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults ...
Carlos Roberto Moratelli, Érika F. Cota, Ma...
ET
2007
101views more  ET 2007»
13 years 7 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri