Sciweavers

154 search results - page 5 / 31
» Algorithmic foundations for a parallel vector access memory ...
Sort
View
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
13 years 11 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
ARC
2010
Springer
387views Hardware» more  ARC 2010»
14 years 2 months ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides
WOMPAT
2001
Springer
13 years 12 months ago
A Study of Implicit Data Distribution Methods for OpenMP Using the SPEC Benchmarks
In contrast to the common belief that OpenMP requires data-parallel extensions to scale well on architectures with non-uniform memory access latency, recent work has shown that it ...
Dimitrios S. Nikolopoulos, Eduard Ayguadé
SPAA
2005
ACM
14 years 1 months ago
Efficient algorithms for verifying memory consistency
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It ha...
Chaiyasit Manovit, Sudheendra Hangal
ICML
1997
IEEE
14 years 8 months ago
Predicting Multiprocessor Memory Access Patterns with Learning Models
Machine learning techniques are applicable to computer system optimization. We show that shared memory multiprocessors can successfully utilize machine learning algorithms for mem...
M. F. Sakr, Steven P. Levitan, Donald M. Chiarulli...