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» Aligators for Arrays (Tool Paper)
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FPL
2004
Springer
87views Hardware» more  FPL 2004»
14 years 27 days ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood
OSDI
2008
ACM
14 years 7 months ago
Carnegie Mellon's CyDAT: Harnessing a Wide Array of Telemetry Data to Enhance Distributed System Diagnostics
The number and complexity of distributed applications has exploded, and to-date, each has had to create its own method for providing diagnostic tools and performance metrics. Thes...
Chas DiFatta, Mark Poepping, Daniel V. Klein
AHS
2007
IEEE
252views Hardware» more  AHS 2007»
14 years 1 months ago
A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
Wing On Fung, Tughrul Arslan, Sami Khawam
TACAS
1998
Springer
98views Algorithms» more  TACAS 1998»
13 years 11 months ago
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
Miroslav N. Velev, Randal E. Bryant
PPOPP
2006
ACM
14 years 1 months ago
Programming for parallelism and locality with hierarchically tiled arrays
Tiling has proven to be an effective mechanism to develop high performance implementations of algorithms. Tiling can be used to organize computations so that communication costs i...
Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheo...