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» An Access Timing Measurement Unit of Embedded Memory
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144
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TC
2010
14 years 10 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
CONCURRENCY
2006
140views more  CONCURRENCY 2006»
15 years 3 months ago
An efficient memory operations optimization technique for vector loops on Itanium 2 processors
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
JEC
2006
107views more  JEC 2006»
15 years 3 months ago
A dynamically reconfigurable cache for multithreaded processors
Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance...
Alex Settle, Dan Connors, Enric Gibert, Antonio Go...
144
Voted
SCOPES
2004
Springer
15 years 9 months ago
Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization
For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of en...
Heiko Falk, Manish Verma
152
Voted
IPSN
2010
Springer
15 years 10 months ago
Distributed estimation of linear acceleration for improved accuracy in wireless inertial motion capture
Motion capture using wireless inertial measurement units (IMUs) has many advantages over other techniques. Achieving accurate tracking with IMUs presents a processing challenge, e...
A. D. Young, M. J. Ling, D. K. Arvind