Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
In a previous paper [Shoshani et al 99], we described a system called STACS (Storage Access Coordination System) for High Energy and Physics (HEP) experiments. These experiments g...
Arie Shoshani, Alex Sim, Luis M. Bernardo, Henrik ...
Today's processors provide a rich source of statistical information on application execution through hardware counters. In this paper, we explore the utilization of these sta...
Kai Shen, Ming Zhong, Sandhya Dwarkadas, Chuanpeng...
The use of asymmetric multi-core processors with onchip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise...
M. Mustafa Rafique, Benjamin Rose, Ali Raza Butt, ...
Recent advance in scalable video coding (SVC) makes it possible for users to receive the same video with different qualities. To adopt SVC in P2P streaming, two key design questio...