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» An Algorithm for Locating Logic Design Errors
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MINENET
2005
ACM
14 years 28 days ago
Shrink: a tool for failure diagnosis in IP networks
Faults in an IP network have various causes such as the failure of one or more routers at the IP layer, fiber-cuts, failure of physical elements at the optical layer, or extraneo...
Srikanth Kandula, Dina Katabi, Jean-Philippe Vasse...
SLIP
2005
ACM
14 years 27 days ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
CCE
2004
13 years 7 months ago
Optimization under uncertainty: state-of-the-art and opportunities
A large number of problems in production planning and scheduling, location, transportation, finance, and engineering design require that decisions be made in the presence of uncer...
Nikolaos V. Sahinidis
INTEGRATION
2000
71views more  INTEGRATION 2000»
13 years 7 months ago
A hardware implementation of realloc function
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Objectoriented applications oft...
Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chan...
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
13 years 11 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...