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» An Architecture for Compressive Imaging
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HPCA
2000
IEEE
15 years 10 months ago
Register Organization for Media Processing
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
Scott Rixner, William J. Dally, Brucek Khailany, P...
ICASSP
2010
IEEE
15 years 4 months ago
A distributed psycho-visually motivated Canny edge detector
This paper proposes a distributed Canny edge detection algorithm which can be mapped onto multi-core architectures for high throughput applications. In contrast to the conventiona...
Srenivas Varadarajan, Chaitali Chakrabarti, Lina J...
ICIP
2008
IEEE
16 years 19 days ago
Hardware-friendly descreening
Conventional electrophotographic printers tend to produce Moir´e artifacts when used for printing images scanned from printed material such as books and magazines. We propose a n...
Hasib Siddiqui, Mireille Boutin, Charles A. Bouman
TVCG
2008
93views more  TVCG 2008»
15 years 6 months ago
Interactive, Internet Delivery of Visualization via Structured Prerendered Multiresolution Imagery
Abstract-We present a novel approach for latency-tolerant remote visualization and rendering where client-side frame rate display performance is independent of source dataset size,...
Jerry Chen, Ilmi Yoon, Wes Bethel
CODES
2002
IEEE
15 years 11 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh