Sciweavers

1322 search results - page 208 / 265
» An Architecture for Distributed Simulation Games
Sort
View
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 19 days ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
ISORC
2002
IEEE
14 years 19 days ago
Service Differentiation in Real-Time Main Memory Databases
The demand for real-time database services has been increasing recently. Examples include sensor data fusion, stock trading, decision support, web information services, and data-i...
Kyoung-Don Kang, Sang Hyuk Son, John A. Stankovic
SPAA
2010
ACM
14 years 16 days ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
IPPS
2000
IEEE
14 years 3 days ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
IPPS
2000
IEEE
14 years 3 days ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
Jim Nilsson, Fredrik Dahlgren