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» An Authorization Logic With Explicit Time
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AMAST
2006
Springer
14 years 2 months ago
State Space Representation for Verification of Open Systems
Abstract. When designing an open system, there might be no implementation available for certain components at verification time. For such systems, verification has to be based on a...
Irem Aktug, Dilian Gurov
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
14 years 27 days ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ITS
2010
Springer
145views Multimedia» more  ITS 2010»
14 years 26 days ago
Predictors of Transfer of Experimental Design Skills in Elementary and Middle School Children
A vital goal of instruction is to enable learners to transfer acquired knowledge to appropriate future situations. For elementary school children in middle-high-SES schools, “exp...
Stephanie Siler, David Klahr, Cressida Magaro, Kev...
CEC
2008
IEEE
14 years 5 months ago
Finding liveness errors with ACO
Abstract— Model Checking is a well-known and fully automatic technique for checking software properties, usually given as temporal logic formulae on the program variables. Most o...
J. Francisco Chicano, Enrique Alba
IFIP
2004
Springer
14 years 4 months ago
The Driving Philosophers
We introduce a new synchronization problem in mobile ad-hoc systems: the Driving Philosophers. In this problem, an unbounded number of driving philosophers (processes) access a rou...
Sébastien Baehni, Roberto Baldoni, Rachid G...