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» An Experimental Analysis of Parallel
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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 10 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
SAC
2004
ACM
15 years 9 months ago
Automatic parallel code generation for tiled nested loops
This paper presents an overview of our work, concerning a complete end-to-end framework for automatically generating message passing parallel code for tiled nested for-loops. It c...
Georgios I. Goumas, Nikolaos Drosinos, Maria Athan...
ICPP
2003
IEEE
15 years 9 months ago
FastLSA: A Fast, Linear-Space, Parallel and Sequential Algorithm for Sequence Alignment
Pairwise sequence alignment is a fundamental operation for homology search in bioinformatics. For two DNA or protein sequences of length ¢ and £ , full-matrix (FM), dynamic prog...
Adrian Driga, Paul Lu, Jonathan Schaeffer, Duane S...
IPPS
2003
IEEE
15 years 9 months ago
Design and Evaluation of a Parallel HOP Clustering Algorithm for Cosmological Simulation
Clustering, or unsupervised classification, has many uses in fields that depend on grouping results from large amount of data, an example being the N-body cosmological simulation ...
Ying Liu, Wei-keng Liao, Alok N. Choudhary
BIRTHDAY
2003
Springer
15 years 9 months ago
Parallel Digital Halftoning by Error-Diffusion
Digital halftoning, or dithering, is the technique commonly used to render a color or grayscale image on a printer, a computer monitor or other bi-level displays. A particular hal...
Panagiotis Takis Metaxas