260 search results - page 44 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
SIGMOD
2003
ACM
14 years 8 months ago
2003
ACM
Increasingly pervasive networks are leading towards a world where data is constantly in motion. In such a world, conventional techniques for query processing, which were developed...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
—Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two...
FCCM
2002
IEEE
14 years 27 days ago
2002
IEEE
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
CAMP
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— Robot vision systems notoriously require large computing capabilities, rarely available on physical devices. Robots have limited embedded hardware, and almost all senso...