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FPGA
2011
ACM
321views FPGA» more  FPGA 2011»
13 years 1 months ago
An analytical model relating FPGA architecture parameters to routability
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
Joydip Das, Steven J. E. Wilton
DAC
2007
ACM
14 years 10 months ago
SODA: Sensitivity Based Optimization of Disk Architecture
Storage plays a pivotal role in the performance of many applications. Optimizing disk architectures is a design-time as well as a run-time issue and requires balancing between per...
Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan
ISCAS
2003
IEEE
93views Hardware» more  ISCAS 2003»
14 years 3 months ago
A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
Bing-Fei Wu, Chung-Fu Lin
ICFEM
1997
Springer
14 years 1 months ago
Refinement of Information Flow Architectures
A calculus is presented for the stepwise refinement of abstract information flow architectures. We give a mathematical model for information flow components based on relations bet...
Jan Philipps, Bernhard Rumpe
DSN
2008
IEEE
14 years 4 months ago
Architectural dependability evaluation with Arcade
This paper proposes a formally well-rooted and extensible framework for dependability evaluation: Arcade (architectural dependability evaluation). It has been designed to combine ...
Hichem Boudali, Pepijn Crouzen, Boudewijn R. Haver...