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DSD
2011
IEEE
194views Hardware» more  DSD 2011»
14 years 5 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
161
Voted
FDL
2007
IEEE
15 years 10 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
186
Voted
ARTMED
2006
158views more  ARTMED 2006»
15 years 6 months ago
CareVis: Integrated visualization of computerized protocols and temporal patient data
Objective: Currently, visualization support for patient data analysis is mostly limited to the representation of directly measured data. Contextual information on performed treatm...
Wolfgang Aigner, Silvia Miksch
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
16 years 12 days ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
ASWSD
2004
Springer
15 years 11 months ago
Simulink Integration of Giotto/TDL
The paper first presents the integration options of what we call the Timing Description Language (TDL) with MathWorks' Simulink tools. Based on the paradigm of logical executi...
Wolfgang Pree, Gerald Stieglbauer, Josef Templ